A huge growth in integrated circuits that are no longer simple electronic circuits has been observed over the past ten years or so: it is predicted that these new integrated circuits, which are already under development, will contain optical functions, high-frequency functions, and even molecular and bio-electronic functions (the term SOC (System On Chip) is often used). However, there are numerous applications in which it is difficult or even possible to produce all the circuits or components providing these various functions on the same homogeneous microtechnological substrate by a single string of technological steps.
A simple solution has consisted in fabricating the components on separate substrates and then assembling them one by one onto the same substrate forming a support by bonding using an additional material, for example a metallic or epoxy material, using the overturning technique known as “flip-chip”, and the like. This solution is satisfactory for a certain number of applications but in particular does not allow for the miniaturization of large scale integrated circuits.
Another solution has consisted in providing substrates that are no longer homogeneous but feature areas having different properties enabling the production of different components.
This explains why, for certain applications, and more particularly for the integration into a structure of so-called “vertical” components conjointly with components that are totally insulated, it has been proposed to produce a mixed substrate (or “patterned” substrate, that is to say a substrate having a buried mixed layer featuring patterns of different materials), that is to say a substrate in which two types of areas co-exist: 1) areas having the properties of a bulk material between the faces of the substrate (for the “vertical” components), and 2) SOI (Silicon On Insulator) type areas, i.e. areas including silicon on top of an insulator such as an oxide).
The bulk materials provide better electrical conduction (between the front face and the rear face of the substrate) as well as, given the absence of any significant thermal barrier, better thermal conductivity (whence better dissipation of heat) than SOI type areas or substrates. They are therefore entirely appropriate in particular for the fabrication of “vertical” components (in particular power components).
SOI areas, on the other hand, have the advantage of enabling the production of totally insulated components (such as fully depleted MOS transistors) and other microelectronic components (in particular logic circuits), for example.
These mixed substrates in theory have numerous advantages, for numerous applications, among which there may be cited in particular:
1) integration of DRAM memories onto a substrate including SOI areas (the dynamic operation of DRAM memories on an SOI substrate is disturbed by the floating potential of that SOI substrate, and so it is preferable to produce these memories in bulk areas alongside SOI areas),
2) integration of power components on SOI (the integration of components on SOI substrates is not possible because of the architecture of these components (this is the case in particular of VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) components), especially as the layer of insulator of an SOI substrate would be a thermal barrier that would prevent sufficient dissipation of the heat generated at the core of the component), and
3) integration of MEMS and new component architectures for the fabrication of sensors, opto-electronic circuits, and the like.
In fact, these mixed substrates can be produced by oxidation of buried layers or by formation of oxide patterns on the surface of a substrate to which another substrate is subsequently bonded.
Direct bonding (often referred to as molecular bonding) is particularly suitable for this purpose, since this type of bonding is in theory capable of providing very high mechanical strength, high thermal conductivity, a uniform thickness of the bonding interface, etc. This type of bonding is effected without additional material (thus without adhesive). Simple surface preparation can in theory suffice to achieve such bonding (it can nevertheless be difficult), even at room temperature. The bringing of the surfaces to be bonded into contact is generally followed by a strengthening (or consolidating) heat treatment.
More precisely, it is known that direct bonding enables thin layers to be transferred onto a substrate. One of the key steps during such transfer of a thin layer onto a substrate is in practice the couple comprising (bringing the surfaces into contact)+(heat treatment to strengthen the bonding interface). In effect, during this heat treatment, bonding defects can appear in the form of areas that have not bonded: these defects can be reflected, for example, in the appearance of native oxide precipitates and/or gas molecules trapped upon bringing into contact the two wafers (namely the layer and the substrate), which can be of silicon (or another material).
It is to be noted that, according to PCT Publication No. WO-2004/059711 (Fournel et al.) concerning the production of mixed structures, the presence of oxide areas at the bonding interface can serve to trap impurities and adsorb them during the heat treatment to consolidate the bonding.
It is as well to note here that, for certain applications, the requirement may be to transfer a layer of silicon onto a silicon substrate via a thin oxide layer rather than directly. According to the document PCT Publication No. WO-2004/059711 cited above, during the heat treatment, the impurities trapped when bringing the wafers into contact can be adsorbed by the oxide layer. Nevertheless, if that layer is very thin, it cannot adsorb all the various impurities, and bonding defects occur anyway in the form of areas that have not bonded. On the other hand, it is clear that the co-existence in a substrate of SOI type areas having different oxide thicknesses could solve the problem of outgassing the impurities, by increasing the thickness of the oxide layer where that is not a problem for the components. This corresponds to another type of mixed structure.
It is therefore clear that it could be of benefit to know how to produce, in particular, two types of “patterned” or mixed structures (or substrates): 1) partial SOI substrate (co-existence of SOI areas and bulk areas), 2) mixed SOI substrate (co-existence of two types of SOI areas, with different buried oxide thicknesses).
In fact, these two types differ in the presence or absence of a continuous oxide layer between the upper and lower portions of the structure.
It is furthermore clear that there could be a benefit in being able to modify other characteristics of the mixed substrate described hereinabove: 1) the possibility of employing different materials (thermal and/or deposited SiO2, Si3N4, Al2O3, AlN and other insulative materials) as buried insulation; and 2) the possibility of using other materials (Si, but also SiGe, GaAs, GaN, InP and other materials) on either side of the continuous or non-continuous buried insulation layer, in particular for the transferred layer and for the substrate to which that layer is bonded (if the structure is obtained by direct bonding).
More generally, it can be of benefit to obtain a mixed structure, i.e. one having a buried layer made up of areas of different materials enabling local modification of the electrical and/or thermal and/or mechanical and/or optical and/or chemical properties of the structure.
As indicated hereinabove, different technologies exist for producing mixed or partial SOI, in particular by oxidation of a substrate below the surface or by bonding (in practice direct bonding) of a plurality of layers or substrates.
Local Implantation SIMOX Technology
The SIMOX (Separation by IMplantation of OXygen) process is known for its simplicity in the production of SOI substrates. In order to obtain an SOI substrate, a very high dose of oxygen is implanted below the “upper” surface of a silicon wafer (or substrate), after which the combination is annealed at a high temperature to convert the region implanted with oxygen into silicon dioxide SiO2.
This technology can enable the production of mixed substrates: using the known techniques of masking and lithography, it is in effect possible to implant the oxygen ions in a localized manner, and thus to create localized underlying oxide layers (see U.S. Patent Publication No. 2006/0040476, U.S. Pat. No. 6,846,727 or the paper “Fabrication of High Quality Patterned SOI Materials by Optimized Low-Dose SIMOX”, Dong et al., pages 60-61, “2004 IEEE International SOI Conference 2004”).
The fabrication of a patterned substrate (or structure) using the SIMOX process thus consists in:
1) depositing a hard mask on a substrate,
2) opening implantation windows in that mask (by lithographic means),
3) implanting oxygen ions through these windows,
4) carrying out an oxidation annealing in order to form localized buried oxide areas, and
5) eliminating the mask.
This process nevertheless has limitations in terms of choice of materials and cannot produce hybrid structures (germanium on silicon, GaN on silicon, silicon on glass, and the like) or in terms of crystallographic structure (for example amorphous layers). In fact, only the formation of silicon dioxide has been thoroughly investigated, although tests with implantation of nitrogen have verified the formation of silicon nitride.
This approach also has various drawbacks or problems:
1) limited choice of oxide: SiO2 by implantation of oxygen and SiN by implantation of nitrogen, whereas many other materials may be desirable,
2) limited choice of material for the whole of the structure in which the insulative patterns are formed (silicon, in practice),
3) surface deformation after implantation and after oxidation annealing (oxidation implies a local increase in the volume of the areas in which oxygen combines with silicon, and consequently “surface swelling”),
4) presence of transitions between SOI areas and bulk areas featuring a high density of defects, and
5) great difficulty in obtaining in a controlled manner mixed SOI type structures (such as SOI type substrates with an oxide layer the thickness whereof varies from one area to another).
Another, more exploratory approach has been proposed by Terada et al. (“A New DRAM Cell with a Transistor on a Lateral Epitaxial Silicon Layer (TOLE Cell)”, pages 2052-2057, in IEEE Transactions on Electron Devices Vol 37, No. 7, September 1990). According to that document, a thermal oxide layer is formed on a silicon substrate; lithographic process steps are carried out in order to etch the oxide layer locally; lateral epitaxial regrowth is then effected; a final polishing removes the silicon and planarizes the surface. However, the choice of materials for producing this structure is limited (to enable the compatibility necessary for epitaxial regrowth). The thicknesses employed are also limited, especially if the structure is heterogeneous.
Mixed or Partial SOI Substrates Obtained by Direct Bonding
The principle of producing mixed structures by direct bonding is described in particular in the PCT Publication No. WO-2004/059711 cited above, but also in U.S. Pat. No. 5,691,231 the preamble whereof describes various known solutions, or in the chapter “Dielectric Isolation Technologies and Power ICs” by Y. Sugawara in “Smart Power ICs” by Muvavi, Bevotti and Vignola.
The first step is to create a cavity in a silicon substrate and then to oxidize the whole of the surface. Chemical mechanical polishing (CMP) removes a portion of the oxide and exposes both Si areas and SiO2 areas, so as to obtain a mixed surface. After chemical cleaning, another silicon substrate is bonded to this mixed surface and then thinned, which yields the required mixed substrate. Trenches can then be formed to complete the insulation of an area of substrate along the local insulation layer.
In a variant referred to by Sugawara (see above), a doped area can be formed (by implantation) at the bottom of the cavity before filling it by oxidation.
These approaches run into a major problem that is linked to the polishing of the mixed surface formed by the mixed Si/SiO2 areas: the conjoint presence of Si and SiO2 areas coexisting on the surface makes planarization of the surface to enable good direct bonding difficult, although it is clear that, in all cases where direct bonding is required, flatness is essential and that the quality of polishing is critical.
Now, at present there is no method for polishing a mixed surface having both silicon areas and silicon oxide areas enabling a compatible surface (in particular in terms of flatness, roughness and homogeneous hydrophilic character) to be obtained compatible with direct bonding of good quality.
In general, the speed of polishing silicon oxide is lower than that of polishing silicon. A phenomenon known as “dishing” then occurs, corresponding to the formation of a negative difference in level (suggestive of a dish) in the region of the silicon areas. Positive differences in level can also persist on the surface (small bumps are obtained), for example linked to defective polishing. This negative or positive difference in level can reach tens of nanometers, as a function in particular of the polishing conditions and the size of the oxide and/or silicon areas. In both cases, the surface irregularities can prevent direct bonding of very good quality and the production yield of such bonded assemblies can be very low.
Moriceau et al., in the paper “Transfer of patterned Si and SiO2 layers for the fabrication of Patterned and Mixed SOI”, pp 203-204, 2004 IEEE International SOI Conference, 10/04, commented on this polishing problem whilst stating that it was possible to solve the difference in level problem, relatively unimportant on the sub-micron scale but routinely observed in the case of patterns having dimensions of the order of one micron or even of one millimeter, by optimizing the polishing processes for each mixed substrate configuration (distribution of the patterns formed by the areas, size of areas, thickness of oxide, and the like). However, this implies that it is not always possible to avoid these polishing problems if the various parameters mentioned above cannot be modified.
For the fabrication of a mixed structure including a vertical component and its control circuit, Hiromasa et al., in Japanese Patent No. JP-08-330554, teach setting back the silicon oxide layer in the cavity relative to the silicon surface, noting that this way there are no bonding defects in the area of the vertical component. However, it is clear that with this approach the bonding interface is not continuous, so that gas molecules can be trapped after bringing the two wafers into contact. This has the drawback that these molecules can lead to partial and unintentional separation of the transferred layer. The lack of continuity also leads to a low thermal conductivity of the assembly.
To get around the impact of differences in level created when polishing on the quality of the bonding of a mixed structure, U.S. Pat. No. 5,691,231 cited above proposes using a polycrystalline silicon layer after the formation of an oxide. Initially, cavities filled with oxide are formed on the surface of a silicon substrate. The whole is then polished. A polysilicon layer is then deposited on the planarized mixed surface and then polished. Another substrate is bonded to it, after which the original substrate is thinned to the required final thickness (typically a few microns).
It is possible with this approach to use silicon substrates having different properties (in terms of doping, for example). These layers nevertheless remain separated by a polysilicon layer, which can be a problem for certain applications.
Another solution relating to direct bonding is also referred to in the document cited above by Sugawara (proposed by Ohata et al. in Tech of IEEE Costume IC Conference, p 443 (1986)). In that approach, a lithographic mask is deposited on an SOI type substrate after a direct bonding step; the upper layer of silicon, the oxide and the solid silicon substrate (in part) are then etched to form a cavity. Epitaxial regrowth of silicon is then effected, with a thickness greater than the thickness of the cavity. Given that the epitaxial regrowth also occurs on the upper layer of silicon, CMP polishing is effected in order to eliminate this overthickness formed on the SOI area. It is nevertheless clear that this technology is complex and of limited application.
Given the state of the art described hereinabove, it is clear that there is no “universal” approach for producing mixed or “patterned” substrates, such as substrates having a buried mixed layer with patterns of different materials and in particular one of which at least is a crystalline material, offering the following performance:
1) the possibility of placing different materials at the same level as, above and below this mixed layer,
2) the possibility of managing different thicknesses (and more particularly the possibility of obtaining thin layers), and
3) the possibility of producing micrometric and millimetric patterns at the same time on the same substrate.